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eproclock ? pci-express gen 2 clock generator SL28PCIE10 ....................................... document #: rev 1.1 page 1 of 16 400 west cesar chavez, austin, tx 78701 1+( 512) 416-8500 1+(512) 416-9669 www.silabs.com features ? one programmable spreadable single-ended clock ? pci-express gen 2 compliant ? low power push-pull type differential output buffers ? integrated voltage regulator ? integrated resistors on differential clocks ? scalable low voltage vdd_io (3.3v to 1.05v) ? wireless friendly 3-bits slew rate control on single-ended clocks. ? four 100mhz differential clocks ? 27mhz video clock ? buffered reference clock 25mhz ? eproclock ? programmable technology ?i 2 c support with readback capabilities ? triangular spread spectrum profile for maximum electromagnetic interference (emi) reduction ? industrial temperature -40 o c to 85 o c ? 3.3v power supply ? 32-pin qfn package 100mhz 48m ref 27m programmable single-ended clock x4 x1 x1 x1 x1 block diagram pin configuration sclock sdata ref vdd_ref xin xout vss_ref ckpwrgd/pd# 32 31 30 29 28 27 26 25 vdd 124 vdd_src vss 223 src3 nc 322 src3# nc 421 vss_src vdd_27 520 src2 27m_nss 619 src2# prog_se 718 vdd_src_io vss_27 817 vdd_src 9 10111213141516 vss_src src0 src0# vss_src src1 src1# vdd_src_io oe#_src2_src3 SL28PCIE10
SL28PCIE10 .......................................document #: rev 1.1 page 2 of 16 32-qfn pin definitions programmable single ended clock SL28PCIE10 allows flexibility of programming any frequency at single ended output prog_se. prog_se can be factory programmed to any frequency as required by the end user with a 3.3v swing single ended output. this clock can have a f eature of spread spectrum to reduce emi. pin no. name type description 1 vdd pwr 3.3v power supply 2 vss gnd ground 3 nc nc no connect. 4 nc nc no connect. 5 vdd_27 pwr 3.3v power supply 6 27m_nss o,se non-spread 27mhz video clock output 7 prog_se o, se spreadable programmable single-ended clock output 8 vss_27 gnd ground 9 vss_src gnd ground 10 src0 o, dif 100mhz true differential serial reference clock 11 src0# o, dif 100mhz complement differential serial reference clock 12 vss_src gnd ground 13 src1 o, dif 100mhz true differential serial reference clock 14 src1# o, dif 100mhz complement differential serial reference clock 15 vdd_src_io pwr scalable 3.3v to 1.05v power supply for output buffer 16 oe#_src2_src3 i 3.3v tolerance input to disable output on pin 7 and pin 8 17 vdd_src pwr 3.3v power supply 18 vdd_src_io pwr scalable 3.3v to 1.05v power supply for output buffer 19 src2# o, dif 100mhz true differential serial reference clock 20 src2 o, dif 100mhz complement differential serial reference clock 21 vss_src gnd ground 22 src3# o, dif 100mhz true differential serial reference clock 23 src3 o, dif 100mhz complement differential serial reference clock 24 vdd_src pwr 3.3v power supply 25 ck_pwrgd/pd# i 3.3v lvttl input. after ck_pwrgd (active high) assertion, this pin becomes a real-time input for asserting power down (active low) 26 vss_ref gnd ground 27 xout o, se 25mhz crystal output 28 xin i 25mhz crystal input 29 vdd_ref pwr 3.3v power supply for outputs and also maintains smbus registers during power-down 30 ref pd, i/o reference 25mhz clock output 31 sdata i/o smbus compatible sdata 32 sclk i smbus compatible sclock
SL28PCIE10 .......................................document #: rev 1.1 page 3 of 16 eproclock ? programmable technology eproclock ? is the world?s first non-volatile programmable clock. the eproclock ? technology allows board designer to promptly achieve optimum compliance and clock signal integrity; historically, attainable typically through device and/or board redesigns. eproclock ? technology can be configured through smbus or hard coded. features: - > 4000 bits of configurations - can be configured through smbus or hard coded - custom frequency sets - differential skew control on true or compliment or both - differential duty cycle contro l on true or compliment or both - differential amplitude control - differential and single-ended slew rate control - program internal or external series resistor on single-ended clocks - program different spread profiles - program different spread modulation rate serial data interface to enhance the flexibility and func tion of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions, such as individual clock output buffers are individually enabled or disabled. the registers associated with the se rial data interface initialize to their default setting at power-up. the use of this interface is optional. clock device register changes are normally made at system initialization, if any ar e required. the interface cannot be used during system operation for power management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write, and block read opera tions from the controller. for block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. for byte write and byte read operations, the system controller can access individually indexed bytes. the offset of the indexed byte is encoded in the command code described in ta ble 1 . the block write and block read protocol is outlined in table 2 while table 3 outlines byte write and byte read protocol. the slave receiver address is 11010010 (d2h). . table 1. command code definition bit description 7 0 = block read or block write operation, 1 = byte read or byte write operation (6:0) byte offset for byte read or byte wr ite operation. for block read or block writ e operations, these bits should be '0000000 ' table 2. block read and block write protocol block write protocol block read protocol bit description bit description 1start 1start 8:2 slave address?7 bits 8:2 slave address?7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code?8 bits 18:11 command code?8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 byte count?8 bits 20 repeat start 28 acknowledge from slave 27:21 slave address?7 bits 36:29 data byte 1?8 bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 45:38 data byte 2?8 bits 37:30 byte count from slave?8 bits 46 acknowledge from slave 38 acknowledge .... data byte /slave acknowledges 46:39 data byte 1 from slave?8 bits .... data byte n?8 bits 47 acknowledge .... acknowledge from slave 55:48 data byte 2 from slave?8 bits .... stop 56 acknowledge .... data bytes from slave / acknowledge .... data byte n from slave?8 bits .... not acknowledge
SL28PCIE10 .......................................document #: rev 1.1 page 4 of 16 .... stop table 3. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1start 1start 8:2 slave address?7 bits 8:2 slave address?7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code?8 bits 18:11 command code?8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 data byte?8 bits 20 repeated start 28 acknowledge from slave 27:21 slave address?7 bits 29 stop 28 read 29 acknowledge from slave 37:30 data from slave?8 bits 38 not acknowledge 39 stop table 2. block read and block write protocol (continued) block write protocol block read protocol bit description bit description
SL28PCIE10 .......................................document #: rev 1.1 page 5 of 16 control registers byte 0: control register 0 bit @pup name description 7 hw reserved reserved 6 0 reserved reserved 5 1 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 0 reserved reserved 0 1 pd_restore save configuration when pd# is asserted 0 = config. cleared, 1 = config. saved byte 1: control register 1 bit @pup name description 7 1 reserved reserved 6 0 pll1_ss_dc select for down or center ss 0 = down spread, 1 = center spread 5 0 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 1 reserved reserved 1 0 reserved reserved 0 1 reserved reserved byte 2: control register 2 bit @pup name description 7 1 ref_oe output enable for ref 0 = output disabled, 1 = output enabled 6 1 reserved reserved 5 1 reserved reserved 4 1 reserved reserved 3 1 reserved reserved 2 1 reserved reserved 1 1 reserved reserved 0 1 reserved reserved byte 3: control register 3 bit @pup name description 7 1 reserved reserved 6 1 reserved reserved 5 1 reserved reserved 4 1 reserved reserved 3 1 reserved reserved 2 1 reserved reserved 1 1 reserved reserved
SL28PCIE10 .......................................document #: rev 1.1 page 6 of 16 0 1 reserved reserved byte 3: control register 3 byte 4: control register 4 bit @pup name description 7 1 reserved reserved 6 1 src0_oe output enable for src0 0 = output disabled, 1 = output enabled 5 1 src1_oe output enable for src1 0 = output disabled, 1 = output enabled 4 1 reserved reserved 3 1 src3_oe output enable for src3 0 = output disabled, 1 = output enabled 2 1 src2_oe output enable for src2 0 = output disabled, 1 = output enabled 1 1 pll1_ss_en enable pll1s spread modulation, 0 = spread disabled, 1 = spread enabled 0 1 reserved reserved byte 5: control register 5 bit @pup name description 7 0 reserved reserved 6 0 reserved reserved 5 0 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved 1 0 reserved reserved 0 0 reserved reserved byte 6: control register 6 bit @pup name description 7 0 reserved reserved 6 0 reserved reserved 5 0 ref bit1 ref slew rate control (see byte 13 for slew rate bit 0 and bit 2) 0 = high, 1 = low 4 0 reserved reserved 3 0 27mhz bit 1 27mhz slew rate control (see byte 13 for slew rate bit 0 and bit 2) 0 = high, 1 = low 2 0 reserved reserved 1 0 reserved reserved 0 0 reserved reserved byte 7: vendor id bit @pup name description 7 0 rev code bit 3 revision code bit 3 6 1 rev code bit 2 revision code bit 2
SL28PCIE10 .......................................document #: rev 1.1 page 7 of 16 5 0 rev code bit 1 revision code bit 1 4 0 rev code bit 0 revision code bit 0 3 1 vendor id bit 3 vendor id bit 3 2 0 vendor id bit 2 vendor id bit 2 1 0 vendor id bit 1 vendor id bit 1 0 0 vendor id bit 0 vendor id bit 0 byte 7: vendor id byte 8: control register 8 bit @pup name description 7 1 device_id3 reserved 6 0 device_id2 reserved 5 0 device_id1 reserved 4 0 device_id0 reserved 3 0 reserved reserved 2 0 reserved reserved 1 1 27m_non-ss_oe output enable for 27m_non-ss 0 = output disabled, 1 = output enabled 0 1 prog_se_oe output enable for prog_se 0 = output disabled, 1 = output enabled byte 9: control register 9 bit @pup name description 7 0 reserved reserved 6 0 reserved reserved 5 1 reserved reserved 4 0 test _mode_sel test mode select either ref/n or tri-state 0 = all outputs tri-state, 1 = all output ref/n 3 0 test_mode_entry allows entry into test mode 0 = normal operation, 1 = enter test mode(s) 2 1 i2c_vout<2> amplitude confi gurations differential clocks i2c_vout[2:0] 000 = 0.30v 001 = 0.40v 010 = 0.50v 011 = 0.60v 100 = 0.70v 101 = 0.80v (default) 110 = 0.90v 111 = 1.00v 1 0 i2c_vout<1> 0 1 i2c_vout<0> byte 10: control register 10 bit @pup name description 7 0 reserved reserved 6 0 reserved reserved 5 0 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 0 reserved reserved
SL28PCIE10 .......................................document #: rev 1.1 page 8 of 16 byte 13: control register 13 1 1 reserved reserved 0 1 reserved reserved byte 10: control register 10 (continued) bit @pup name description byte 11: control register 11 bit @pup name description 7 0 reserved reserved 6 0 reserved reserved 5 0 reserved reserved 4 0 reserved reserved 3 0 reserved reserved 2 1 reserved reserved 1 1 reserved reserved 0 1 reserved reserved byte 12: byte count bit @pup name description 7 0 bc7 byte count register for block read operation. the default value for byte count is 15. in order to read beyond byte 15, the user should change the byte count limit.to or beyond the byte that is desired to be read. 60 bc6 50 bc5 40 bc4 31 bc3 21 bc2 11 bc1 01 bc0 bit @pup name description 7 1 ref_bit2 drive strength control - bit[2:0], note: see byte 6 bit 5 for ref slew rate bit 1 and byte 6 bit 3 for 27mhz slew rate bit 1 normal mode default ?101? wireless friendly mode default to ?111? 61 ref_bit0 5 1 27mhz_nss_bit2 4 1 27mhz_nss_bit0 3 1 prog_se_bit2 2 1 prog_se_bit0 1 0 reserved reserved 0 0 wireless friendly mode wireless friendly mode 0 = disabled, default all single-ended clocks slew rate config bits to ?101? 1 = enabled, default all single-ended clocks slew rate config bits to ?111?
SL28PCIE10 .......................................document #: rev 1.1 page 9 of 16 byte 14: control register 14 . . pd# (power down) clarification the ck_pwrgd/pd# pin is a dual-function pin. during initial power up, the pin functions as ck_pwrgd. once ck_pwrgd has been sampled high by the clock chip, the pin assumes pd# functionality. the pd# pin is an asynchronous active low input used to shut off all clocks cleanly before shutting off power to the device. this signal is synchronized internally to the device before powering down the clock synthesizer. pd# is al so an asynchronous input for powering up the system. when pd# is asserted low, clocks are driven to a low value and held before turning off the vcos and the crystal oscillator. pd# assertion when pd# has been sampled low by the internal reference clock all differential clocks will be stopped in a glitch free manner to the low/low state within their next two consec- utive rising edges. when pd# is sampled low by two consecutive cycles of an internal reference clock, all single-ended outputs will be held low on their next high-to-low transition. pd# deassertion power up latency will be less than 2ms for crystal input reference clock and less than 8ms for differential input reference clock. this is the delay from the power supply reaching the min value specifie d in the datasheet, until the time that the part is ready to sample any latched inputs on the first rising edge of ckpwrgd. after the first rising edge on ckpwrgd this pin becomes pd#. after a valid rising edge on ckpwrgd/pd# pin, a time of not more than 1.8ms is allowed for the clock chip?s internal pll?s to power up and lock, after this time all outputs are enabled in a glitch free manner within a few clock cycles of each clock. oe#_src2_src3 assertion the oe#_src2_src3 signal is an active low input used for synchronous stopping and starting the src2 and src3 output clocks while the rest of the clock genera tor continues to function. when the oe#_src2_s rc3 pin is asserted, all cpu outputs that are set with the smbus configuration to be stoppable are stopped cleanly. the final states of the stopped cpu signals are cput = high and cpuc = low. oe#_src2_src3 deassertion the deassertion of the oe#_src2_src3 signal causes all stopped src2 and src3 outputs to resume normal operation in a synchronous manner. no short or stretched clock pulses are produced when the clock resumes. the maximum latency from the deasse rtion to active outputs is no more than two src clock cycles. bit @pup name description 7 1 reserved reserved 6 0 reserved reserved 5 1 reserved reserved 40 otp_4 otp_id identification for programmed device 30 otp_3 20 otp_2 10 otp_1 00 otp_0 table 4. output driver status during oe#_src2_src3 oe#_src2_src3 as- serted smbus oe disabled single-ended clocks stoppable running driven low non stoppable running differential clocks stoppable clock driven high clock driven low clock# driven low non stoppable running table 5. output driver status all single-ended clocks all differential clocks w/o strap w/ strap clock clock# pd# = 0 (power down) low hi-z low low
SL28PCIE10 .....................................docume nt #: rev 1.1 page 10 of 16 absolute maximum conditions parameter description condition min. max. unit v dd_3.3v main supply voltage ? 4.6 v v dd_io io supply voltage 4.6 v v in input voltage relative to v ss ?0.5 4.6 v dc t s temperature, storage non-functional ?65 150 c t a temperature, operating ambient functional -40 85 c t j temperature, junction functional ? 150 c ? jc dissipation, junction to case mil-std-883e method 1012.1 ? 20 c/ w ? ja dissipation, junction to ambient jedec (jesd 51) ? 60 c/ w esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? v ul-94 flammability rating at 1/8 in. v?0 multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. dc electrical specifications parameter description condition min. max. unit vdd core 3.3v operating voltage 3.3 5% 3.135 3.465 v v ih 3.3v input high voltage (se) 2.0 v dd + 0.3 v v il 3.3v input low voltage (se) v ss ? 0.3 0.8 v v ihi2c input high voltage sdata, sclk 2.2 ? v v ili2c input low voltage sdata, sclk ? 1.0 v v ih_fs fs input high voltage 0.7 vdd+0.3 v v il_fs fs input low voltage v ss ? 0.3 0.35 v i ih input high leakage current except internal pull-down resistors, 0 < v in < v dd ?5 ? a i il input low leakage current except internal pull-up resistors, 0 < v in < v dd ?5 ? ? a v oh 3.3v output high voltage (se) i oh = ?1 ma 2.4 ? v v ol 3.3v output low voltage (se) i ol = 1 ma ? 0.4 v v dd io low voltage io supply voltage 1 3.465 v i oz high-impedance output current ?10 10 ? a c in input pin capacitance 1.5 5 pf c out output pin capacitance 6pf l in pin inductance ? 7 nh idd_ pd power down current ? 1 ma i dd_3.3v dynamic supply current all outputs enabled. se clocks with 8? traces and 4pf load. differential clocks with 7? traces and 2pf load. ?65ma i dd_vdd_io dynamic supply current all outputs enabled. se clocks with 8? traces and 4pf load. differential clocks with 7? traces and 2pf load. ?25ma
SL28PCIE10 .....................................document #: rev 1.1 page 11 of 16 ac electrical specifications parameter description condition min. max. unit crystal l acc long-term accuracy measured at vdd/2 differential ? 250 ppm clock input t dc clkin duty cycle measured at vdd/2 47 53 % t r /t f clkin rise and fall times measured between 0.2v dd and 0.8v dd 0.5 4.0 v/ns t ccj clkin cycle to cycle jitter measured at vdd/2 ? 250 ps t ltj clkin long term jitter measured at vdd/2 ? 350 ps v ih input high voltage xin / clkin pin 2 vdd+0.3 v v il input low voltage xin / clkin pin ? 0.8 v i ih input high current xin / clkin pin, vin = vdd ? 35 ua i il input low current xin / clkin pin, 0 < vin <0.8 -35 ? ua src at 0.7v t dc src duty cycle measured at 0v differential 45 55 % t period 100 mhz src period measured at 0v differential at 0.1s 9.99900 10.0010 ns t periodss 100 mhz src period, ssc measured at 0v differential at 0.1s 10.02406 10.02607 ns t periodabs 100 mhz src absolute period measured at 0v differential at 1 clock 9.87400 10.1260 ns t periodssabs 100 mhz src absolute period, ssc measured at 0v differential at 1 clock 9.87406 10.1762 ns t skew(window) any src clock skew from the earliest bank to the latest bank measured at 0v differential ? 3.0 ns t ccj src cycle to cycle jitter measured at 0v differential ? 125 ps rms gen1 output pcie* gen1 refclk phase jitter ber = 1e-12 (including pll bw 8 - 16 mhz, = 0.54, td=10 ns, ftrk=1.5 mhz) 0108ps rms gen2 output pcie* gen2 refclk phase jitter includes pll bw 8 - 16 mhz, jitter peaking = 3db, = 0.54, td=10 ns), low band, f < 1.5mhz 03.0ps rms gen2 output pcie* gen2 refclk phase jitter includes pll bw 8 - 16 mhz, jitter peaking = 3db, = 0.54, td=10 ns), low band, f < 1.5mhz 03.1ps l acc src long term accuracy measured at 0v differential ? 100 ppm t r / t f src rising/falling slew rate measured differentially from 150 mv 2.5 8 v/ns t rfm rise/fall matching measured single-endedly from 75 mv ? 20 % v high voltage high 1.15 v v low voltage low ?0.3 ? v v ox crossing point voltage at 0.7v swing 300 550 mv 27m_nss at 3.3v t dc duty cycle measurement at 1.5v 45 55 % t period spread 27m period measurement at 1.5v 37.03594 37.03813 ns t r / t f rising and falling edge rate measured between 0.8v and 2.0v 1.0 4.0 v/ns t ccj cycle to cycle jitter measurement at 1.5v ? 300 ps l acc 27_m long term accuracy measured at crossing point v ox ?50ppm ref t dc ref duty cycle measurement at 1.5v 45 55 %
SL28PCIE10 .....................................docume nt #: rev 1.1 page 12 of 16 test and measurement setup for reference clock the following diagram shows the test load confi gurations for the single-ended ref output signal. t period ref period measurement at 1.5v 39.996 40.004 ns t r / t f ref rising and falling edge rate measur ed between 0.8v and 2.0v 1.0 4.0 v/ns t ccj ref cycle to cycle jitter measurement at 1.5v ? 500 ps l acc long term accuracy measurement at 1.5v ? 50 ppm enable/disable and set-up t stable clock stabilization from power-up ? 1.8 ms t ss stopclock set-up time 10.0 ? ns ac electrical specifications (continued) parameter description condition min. max. unit figure 1. single-ended ref triple load configuration figure 2. single-ended output signals (for ac parameters measurement)
SL28PCIE10 .....................................docume nt #: rev 1.1 page 13 of 16 for differential clock signals this diagram shows the test load configur ation for the differential clock signals figure 3. 0.7v differential load configuration figure 4. differential measurement for differentia l output signals (for ac parameters measurement)
SL28PCIE10 .....................................docume nt #: rev 1.1 page 14 of 16 figure 5. single-ended measurement for differentia l output signals (for ac parameters measurement)
SL28PCIE10 .....................................docume nt #: rev 1.1 page 15 of 16 ordering information part number package type product flow lead-free SL28PCIE10ali 32-pin qfn industrial, -40 ? to 85 ? c SL28PCIE10alit 32-pin qfn?tape and reel industrial, -40 ? to 85 ? c SL28PCIE10alc 32-pin qfn commercial, 0 ? to 85 ? c SL28PCIE10alct 32-pin qfn?tape and reel commercial, 0 ? to 85 ? c this device is pb free and rohs compliant. package diagrams 32-lead qfn 5x 5mm (saw version) sl 28 pcie10 a l i - t temperature designator package designator l : qfn revision number a = 1 st silicon generic part number designated family number company initials packaging designator for tape and reel
SL28PCIE10 .....................................docume nt #: rev 1.1 page 16 of 16 the information in this document is believed to be accurate in all respects at the time of p ublication but is subject to change without notice. sil- icon laboratories assumes no responsibility for errors and omissi ons, and disclaims responsibil ity for any consequences resulti ng from the use of information included herein. additi onally, silicon laboratories assumes no res ponsibility for the functioning of undescr ibed features or parameters. silicon laboratories reserves the right to make c hanges without further notice. silicon laboratories makes no warra nty, repre- sentation or guarantee regarding the suitability of its produc ts for any particular purpose, nor does silicon laboratories assu me any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon labor atories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other a pplication in which the failure of the si licon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or use silicon laboratorie s products for any such unintended or unauthor ized appli- cation, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. document history page document title: SL28PCIE10 pc eproclock ? pci-express gen 2 clock generator document #: sp-ap-0212 (rev. aa) rev. issue date orig. of change description of change 1.0 10/15/10 trp initial release aa 10/22/10 trp 1. updated miscellaneous text content 2. updated absolute maximum value of vdd_io aa 12/2/10 trp 1. updated pd# assertion, oe# _src2_src3 assertion descriptions aa 12/7/10 trp 1. added crystal and clock input ac specifications 2. removed redundant v ixh and v ixl from dc specifications aa 12/15/10 trp 1. updated power down description

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